1. Field of the Invention
The present invention relates to a semiconductor integrated logic circuit, and more specifically to a test circuit for use in a semiconductor integrated logic circuit, for facilitating a test of a circuit generating a control signal used for controlling a tri-state buffer configured to assume a high impedance output condition in addition to a logical high level signal outputting condition and a logical low level signal outputting condition, or a bi-directional (input/output) buffer ordinarily including the tri-state buffer therein.
2. Description of Related Art
For example, Japanese Patent Application Pre-examination Publication No. JP-A-63-070175, the content of which is incorporated by reference in its entirety into this application (an English abstract of JP-A-63-070175 is available from the Japanese Patent Office, and the content of the English abstract of JP-A-63-070175 is incorporated by reference in its entirety into this application), proposes a test method for detecting that, in a logic circuit for generating a control signal for switching a tri-state circuit between an output enable condition (of outputting either a logical high level signal or a logical low level signal) and a high impedance output condition, there occurs such a trouble that an output of the logic circuit is ceaselessly fixed to a logical high level or a logical low level. In this trouble, the output condition of the tri-state buffer an no longer be changed over. For making it possible to detect this type of trouble, a high impedance condition of the tri-state circuit output is added as an expected output value.
Alternatively, Japanese Patent Application Pre-examination Publication No. JP-A-63-295980, the content of which is incorporated by reference in its entirety into this application (an English abstract of JP-A-63-295980 is available from the Japanese Patent Office, and the content of the English abstract of JP-A-63-295980 is incorporated by reference in its entirety into this application), proposes an input/output circuit having such a construction that each input/output buffer of an input/output circuit and an internal circuit of a semiconductor integrated circuit can be electrically separated from each other, and the separated input/output buffer can be electrically connected to another input/output buffer so that in order to detect a possible trouble of the input/output buffer, the output/output buffer can be tested independently of the internal circuit without operating the internal circuit.
The above mentioned prior art for testing the logic circuit for generating the control signal for controlling the output condition of the tri-state circuit has the following problems:
A first problem is that a test circuitry for testing the high impedance condition of a "circuit or a device under test", is seldom used in ordinary cases. The reason for this is as follows:
A procedure for testing the high impedance condition of the "circuit under test", is complicated, with the result that the testing system is expensive. Furthermore, even in a testing system having a function of testing the high impedance condition, the testing of the high impedance condition in the tri-state buffer is conducted in a functional test by checking whether or not the output terminal becomes a logical high level when the output terminal is pulled up to a high level voltage, and then, by checking whether or not the output terminal becomes a logical low level when the output terminal is pulled down to a low level voltage. Namely, the testing of two times is ordinarily required.
A second problem is that although the control of the tri-state buffer can be tested, a logic circuit connected to the control signal cannot be tasted. The reason for this is that, although the tri-state buffer can be tested by supplying another signal to the input of the tri-state buffer as shown in JP-A-63-295980, it is not possible to test an operation of an circuit which is provided before the tri-state buffer and which is typified by the logic circuit for generating the control signal.